This invention relates generally to computers, and more particularly to memory devices and methods of testing such devices.
Computer designers desire fast and reliable memory devices that will allow them to design fast and reliable computers. Manufacturers of memory devices, such as random access semiconductor memories, must test a full range of functionality and timing characteristics of the memory devices in order to provide a reliable product to their customers. Because each memory cell of the device must be tested, the time and equipment necessary for testing memory devices having increasing density represents a significant portion of the overall manufacturing cost of such devices. Any reduction in the time to test each unit will reduce manufacturing costs.
Semiconductor manufacturers have developed fast testing routines to allow a greater number of chips to be tested simultaneously using a given testing device. One known testing routine, Jedec, simply compares the data written to a memory device with the data read from that memory device, and assigns a 1 value to one or more memory cell addresses if the data matches (passes), or a 0 if the data does not match (fails). While the Jedec routine is fast, it does not output the actual data written to the memory device. As a result, if the tester outputs a continuous string of 1 s, indicating that the memory device passes, a technician is unsure whether the device actually passes, or if an error has occurred in the device, or at some point along the path from the device to the tester, to cause such an output.
To compensate for this shortcoming of the Jedec routine, a Micron Test Mode Routine provides three outputs. The Micron Routine outputs the actual data, as a 0 or a 1, and a mid-level tri-state value therebetween. If the tri-state value is output, rather than a 1 or a 0, the technician recognizes that an error has occurred. Unfortunately, while the Micron Routine provides superior testing of most semiconductor devices, the routine typically cannot bias the output back to the tri-state value before the beginning of the next read/write cycle rapidly enough to allow current high-speed memory devices to be tested at their normal operating speed. As a result, such high-speed memory devices must be tested at speeds slower than their typical operating speed.
To save testing time and cost, manufacturers of memory devices increasingly automate the testing procedure so that a tester applies the testing routine simultaneously to several chips. Automated testing is most easily accomplished after the memory device has been packaged as a semiconductor chip, because the chip can be automatically inserted into a test socket using pick and place machinery. Automated testing circuitry then performs the testing routine by applying predetermined voltages and signals to the chip, writing test data patterns to the memory, reading data, and analyzing the results to detect memory speed, timing, failures, etc. The more chips that can be tested simultaneously, the greater testing time savings per chip.
Most testers used in testing semiconductor chips are expensive. For example, a current tester manufactured by Teradyne has 128 input/output (xe2x80x9cI/Oxe2x80x9d) lines. To maximize the number of chips that this tester can test simultaneously, the on-chip data input/output lines, or xe2x80x9cDQ lines,xe2x80x9d are multiplexed so that fewer I/O lines from the tester are required to be coupled to each chip. For example, the tester writes a predetermined data pattern simultaneously to multiple locations in each memory device and then accesses the written data during a read cycle. Comparator circuits fabricated on-chip compare the data read from the multiple locations and indicate whether all the data read matches the data written. If the chip has 32 DQ lines (DQ0-DQ31), on-chip 4:1 multiplexers and testing circuitry compress data onto only 8 of the 32 DQ lines. As a result, only 8 of the 128 lines of the tester are required for each chip. Consequently, the tester""s 128 I/O lines can simultaneously test 16 chips.
In another solution, certain semiconductor memory devices, manufactured by Micron Technology, Inc., provide on-chip test mode circuitry that helps compensate for such delays during testing of devices. Under such test mode circuitry, the external testing device writes data to the chip during a first interval, and then writes the same data again to the DQ lines during a second interval. During the second interval, while the data is written again to the DQ lines, the data previously written to the memory device is read therefrom and latched. On-chip comparators then compare the latched data to the data written during the second interval. If the latched data equals the data written during the second interval, then the chip passes. Such a device can rapidly analyze the read data written to the device.
While the above solutions can detect for typical cell-to-cell defects and functionality of the chip, they cannot accurately test the speed of the chips. As semiconductor memory chips provide increasingly faster data I/O rates, particularly with synchronous DRAMs, data is required to be transferred to and from the chips in as little as 9 nanoseconds or less, based on a 10-nanosecond or faster clock cycle. As a result, such chips provide only a 1-nanosecond margin of error. Today""s increasingly fast memory devices require highly precise generation of timing signals and precise measurement of the memory device""s response thereto. Gate delays caused by the multiplexing circuitry required during testing cause the data to be read from the chips in greater than 10 nanoseconds. As a result, the tester cannot determine if the chip accurately output data within the required 9 nanoseconds. In other words, the on-chip testing circuitry prohibits the tester from testing the speed of such chips.
Obviously, it is desirable to determine the performance, and thus the speed of, semiconductor memory chips, especially high-speed chips. Additionally, because of manufacturing process tolerance and variations, one memory device of a particular design may be faster than another memory device of the very same design. Manufacturers therefore typically also desire to test the speed of such chips so that such chips can be sorted based on speed grades. To provide such speed testing, typical address compression mode testing, and on-chip multiplexing of DQ lines, must be abandoned. As a result, where 16 or more chips could previously be simultaneously tested using multiplexing, only 4 of such chips can be simultaneously speed tested because all 32 DQ lines of each chip must be coupled to the tester""s I/O lines. As a result, there is a need to simultaneously speed test an increasing number of chips using a given tester.
One solution has been to purchase a larger number of testers, or more expensive testers having a greater number of I/O lines. However, as noted above, such testers are quite expensive.
The present invention provides a semiconductor device that can be efficiently speed tested, and which overcomes at least the shortcomings of the prior art discussed above. The memory device requires, at a minimum, only two I/O lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines in address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether the data read from the memory device matches or whether the data does not match. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line. Importantly, the external testing device need not read the data from the first DQ line simultaneously with the test data flags from a second DQ line.
The present invention also embodies a method of reducing the number of compare circuits required in on-chip test circuitry. To reduce the number of exclusive OR gates, and thereby realize increased surface area on the die, compare circuits compare not only bits of a given data word, but also at least one bit from another data word. Therefore, rather than employing two compare circuits that compare first and second data words, and a third compare circuit that compares the results of the first two compare circuits, the present invention avoids the need for the third compare circuit by comparing the first data word in a first compare circuit with at least one bit from the second data word.
In a broad sense, the present invention embodies a semiconductor memory device having a plurality of memory cells, at least first and second output terminals, a control circuit, a test circuit and a data path or switch. The plurality of memory cells are operable to store data therein, and include first and second sub-arrays of memory cells. The first and second output terminals are coupled to the first and second sub-arrays, respectively. The control circuit is coupled to the first and second sub-arrays and is operable to transfer data from the first and second sub-arrays to the first and second output terminals, respectively.
The test circuit is coupled to the control circuit and to the first and second sub-arrays. The test circuit, in response to a test mode signal from the control circuit, tests data written to the first sub-array and outputs a test signal based on the testing. The switch receives the test mode signal from the control circuit and couples the test circuit to the first output terminal in response thereto. As a result, the test signal can be provided to the first output terminal, while data stored in the second sub-array can be provided to the second output terminal during the testing.
Additionally, the present invention embodies a method of testing a semiconductor memory device having at least first and second sub-arrays of memory cells. The method includes the steps of: (a) entering into a test mode; (b) writing data to the first and second sub-arrays; (c) testing the data written to the first sub-array; (d) providing a test signal indicating the results of the testing; (e) selectively providing the test signal to an output terminal when the memory device is in the test mode; and (f) reading the data from the second sub-array and providing the data to a second output terminal.
Moreover, the present invention embodies a semiconductor memory device having a plurality of memory cells, a control circuit and a test circuit. The plurality of memory cells include first and second sets of sub-arrays of memory cells, each set having eight sub-arrays corresponding to a data word. The control circuit is coupled to the plurality of memory cells and is operable to write data to, and read data from, the plurality of memory cells.
The test circuit has first and second compare circuits. The first compare circuit compares bits in a first data word written to the first set of sub-arrays to each other and outputs a pass value for a test signal if all of the bits in the first data word match. The second compare circuit compares bits in a second data word written to the second set of sub-arrays to each other and to at least one bit from the first data word, and outputs a pass value for the test signal if all of the bits of the second data word and the one bit from the first data word match.